RISC-V CPU compiled into Qwen3.5 weights

🤖 RISC-V CPU compiled into Qwen3.5 weights

Divyansh Agrawal built Qwenputer: 11 layers were added to Qwen3.5-4B, compiled into a deterministic 32-bit RISC-V CPU. RAM is the Gated DeltaNet state: with gate=1 and beta=1, one-hot keys write and read matrix rows 1-to-1, with no learning involved. According to the author, the CPU passes riscv-tests and executes C and MicroPython in the forward pass.

🌍 Deterministic logic was compiled into production model weights without fine-tuning: linear RNN layers became addressable RAM, similar to fast weight programmers. Reasoning hidden in RNN state may evade chain-of-thought monitoring.

👤 The 18.8 GB checkpoint is on Hugging Face (divagr1925/Qwen3.5-4B-Qwenputer, Apache-2.0) and runs on a single 24 GB GPU via standard transformers. Downside: each CPU instruction costs several tokens, with timing measured in seconds.

Source 1: https://divagr.com/blog/qwenputer Source 2: https://github.com/divagr18/qwenputer