Developer Divyansh Agrawal has published Qwenputer, an experimental Qwen3.5-4B model into whose weights a compiler has embedded a working 32-bit RISC-V processor. The processor's RAM is the state of the model's own Gated DeltaNet layers, and all CPU weights are computed without any training. During a standard forward pass, the processor executes C and MicroPython programs, and the checkpoint published on Hugging Face under the Apache-2.0 license runs on a single GPU with 24 GB of memory via standard transformers.
What happened
Divyansh Agrawal, known on GitHub as divagr18, built Qwenputer as a modification of Qwen3.5-4B: 11 transformer layers were added before the 32 layers of the base model, implementing a 32-bit deterministic RISC-V processor with the RV32IM instruction set, Zba extension, and a bignum coprocessor. No training is used in the project; the Gated DeltaNet state matrix serves as RAM: with gate=1 and beta=1, one-hot keys write to and read from individual rows of this matrix one-to-one, so data is preserved without distortion. The author reports that the processor passes the official riscv-tests suite and executes C and MicroPython directly during the forward pass, without external runtimes or tool calls. Verifiable metrics: approximately 230,000 output positions were reproduced with zero discrepancies, and the speed is approximately 3,200 CPU tokens per second on an NVIDIA L4. On arithmetic benchmarks, Qwenputer scores 97.5–100% compared to 55–90% for the base Qwen3.5-4B. The 18.8 GB checkpoint contains 9B parameters and runs on a single 24 GB GPU.
Context
The technical foundation of the project is the concept of fast weight programmers (Schlag et al., 2021): the state of linearly recurrent layers can be used as writable memory with direct addressing. In standard models, the state of Gated DeltaNet and similar Mamba-like layers serves as context compression; the author demonstrates that with gate=1 and beta=1, the same state behaves as exact RAM. A second important detail is the difference between compilation and training: the processor weights were not tuned via gradient descent but computed by a compiler, so the CPU behavior is fully deterministic and inference results are reproduced exactly. In this interpretation, Qwenputer is a demonstration of the in-weight compute direction, where part of the computation lives not in external tools but within the model's own weights.
Why this matters for the industry
For the industry, a practical mechanism for compiling deterministic logic directly into the weights of a production model without fine-tuning has been demonstrated: linear RNN layers are transformed into addressable RAM, and part of the computation is executed by the model itself instead of tool calls. The scheme is potentially cheap to transfer because compilation does not require a training run, meaning the technique can be tried on other hybrid architectures with linearly recurrent layers at the level of Gated DeltaNet and Mamba. If the community reproduces the results, forks of the technique, independent benchmarks under batching and quantization, and eventually niche products like verifiable computational layers for agentic pipelines or sandboxes for untrusted code without an external runtime are likely. The project simultaneously sharpens the security question: reasoning hidden in RNN state may evade chain-of-thought monitoring, which will have to be considered when designing agentic systems. For now, this is a research release by a single developer, without a product, customers, or pricing.
Why this matters for users
The model is open for verification: the divagr1925/Qwen3.5-4B-Qwenputer checkpoint is published on Hugging Face under the Apache-2.0 license and runs via standard transformers, requiring only a single 24 GB GPU. For researchers and enthusiasts, this is a ready-made experimental testbed where the author's results can be reproduced and the project's internals studied. A separate educational value lies in the fact that the example clearly shows: state machines on DeltaNet and Mamba-like layers can function as exact addressable memory, not just as context compression. The main barrier to practical application is speed: computations inside the model take seconds, not microseconds, so this mode is currently unsuitable for everyday tasks.
What is currently unknown / limitations
The entire quantitative evidence base, from passing riscv-tests to benchmarks and speed measurements, was published by the author themselves on divagr.com, in the divagr18/qwenputer GitHub repository, and on the Hugging Face model card; there are no independent third-party reproductions at the time of publication, so the author's claim that this is not a joke or simulation currently relies only on their own data. The arithmetic gain is obtained by construction, as arithmetic is executed by the embedded CPU, and it cannot be read as an increase in the model's capabilities. Each CPU instruction costs several decoded tokens, computations take seconds, and no ready-made integrations with major inference stacks have been announced. Finally, while the stated base model has 4B parameters, the checkpoint contains 9B parameters, and the nearly doubled size is itself part of the solution's cost.
Sources
- Qwenputer: a fully functioning, deterministic RISC-V CPU inside Qwen3.5 — Divyansh Agrawal
- GitHub — divagr18/qwenputer: A computer, compiled into the weights of a language model
- divagr1925/Qwen3.5-4B-Qwenputer · Hugging Face
Author
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