SK hynix Unveils AI Memory Roadmap

At SEDEX 2026 in Seoul, SK hynix CDO Ahn Hyun presented a memory roadmap for the AI era: continued HBM development up to HBM4E, custom HBM with customer logic in the base die, 3D Stacked DRAM — placing DRAM directly on GPU/NPU — and HBF, NAND flash with TSV stacking at a level between HBM and SSD.

Compiled by Sergey KostenchukPublished 2026-10-15Updated 2026-10-16

2026-10-15 Coding

💾 SK hynix Unveils AI Memory Roadmap

At SEDEX 2026 in Seoul (October 14), the company's CDO Ahn Hyun outlined the plan: HBM will reach HBM4E, custom HBM with customer logic in the base die will appear, and 3D Stacked DRAM will be placed on GPU/NPU. HBF was separately announced — NAND with TSV stacking between HBM and SSD: the goal is about half the bandwidth of HBM with ~10x the capacity.

🌍 Memory is becoming a bottleneck in AI infrastructure on par with compute: the company expects performance requirements to grow by approximately 20x by 2030 compared to 2026. Its roadmap defines the memory hierarchy for future accelerators and data centers.

👤 This explains why AI services are getting more expensive and why the HBM shortage is impacting markets. The next front is DRAM directly on GPU and flash with HBM-level bandwidth: in the long term, this will reduce the cost and power consumption of inference.

Source 1: https://biz.chosun.com/en/en-it/2026/10/14/75MZQUYQKNCLFKB3HXN5OZJPTQ/

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