On August 31, 2026, Chinese company Hanxu Technology (寒序科技), reportedly founded in August 2023 at Peking University's Center for Applied Magnetism, unveiled uHBM and uLPU architectures for large language model inference. The base Compute-Memory Die combines non-volatile Persistent MRAM with matrix-vector computations: model weights are permanently resident in memory, and only low-dimensional activation vectors cross the die boundary. For the first generation of uHBM, projected targets are stated — up to 24 TB/s of intra-die read bandwidth and over 2,000 tokens/s when decoding a 4-billion-parameter multimodal model, with the company noting that both figures are projected rather than measured. The only independent measurement to date pertains to a different chip, the SpinPU-ED01, which has undergone third-party verification.

What Happened

The announcement is framed as an architectural lineup rather than a finished product. The core is the Compute-Memory Die, in which an array of Persistent MRAM sits alongside matrix-vector computational blocks: model weights are written into magnetoresistive memory and remain resident, so only low-dimensional activation vectors enter and exit the die. In addition to the uHBM-Die, the lineup includes the uLPU chip, memory modules, a 2U tray for 16 uLPU chips, and a rack-scale system; UCIe, LPDDR5X, and GDDR7 interfaces are announced. For the first generation of uHBM, projected metrics are cited — intra-die read bandwidth of up to 24 TB/s and a target of over 2,000 tokens/s when decoding a 4-billion-parameter multimodal model; both figures are designated as projected.

Context

Understanding the announcement is aided by the nature of the workload: during the decode phase of generation, each subsequent token requires re-reading billions of model weights, making the workload read-intensive and bottlenecked not by computation but by weight transfer — a limitation known as the "memory wall." The industry has so far responded by expanding channels and bringing memory closer to computation: HBM3E in GPU systems, Groq's LPU, Samsung's LPDDR5X-PIM — all variants of processing-in-memory. MRAM approaches the problem differently: a bit is stored by the magnetization direction of two ferromagnetic layers across a magnetic tunnel junction, leakage current is nearly zero, switching takes nanoseconds, and the rewrite endurance is practically unlimited — unlike flash memory. The novelty of Hanxu's announcement is more systemic than algorithmic: the "memory wall" and processing-in-memory are long known individually, but the combination of non-volatile MRAM, permanently resident weights, and matrix-vector computations on the same die is a new industrial configuration.

Why This Matters for the Industry

For the industry, this is a claim to a new class of hardware against the "memory wall" of the decode phase: if the architecture survives tape-out, a competitor to HBM will emerge in the inference bandwidth market, and the stated intra-die bandwidth will set a new class of price benchmarks for decode systems and create pressure on the HBM market. For builders, this is a potential path to reducing the cost of latency-critical inference and possible "fast decode" endpoints at cloud providers. Today, the commercial impact is practically zero: there is no product, pricing, or customers, and the value of the announcement lies in the agenda: the direction of "computation on magnetic memory" has gained a concrete example with a verified engineering prototype, so the class of "resident weights in memory" should be included in the watchlist when planning the next generation of inference infrastructure. The checkpoint is the tape-out of the first uLPU and the first measured metrics of an engineering sample.

Why This Matters for Users

For readers, the news is illustrative of how hardware is designed for a specific property of large models rather than as a universal upgrade. If the technology reaches serial products, users of latency-sensitive scenarios — voice assistants, agentic systems, and real-time streaming — will feel the effect: responses will become faster, and fast decoding modes at providers will likely become cheaper. There is no direct benefit today: no SDK, API, pricing, timelines, or developer access exists, so the architecture is not yet an option for product or procurement, but a benchmark of where inference hardware is heading and what to watch for when choosing a provider in upcoming cycles.

What Is Still Unknown / Limitations

The key stated figures are explicitly called projected rather than measured by the company: there is no academic paper, calculation methodology, or comparison with HBM3E or Groq LPU in the sources. The figures are internally consistent, however: decoding a 4-billion-parameter model with 16-bit weights requires roughly 8 GB of reads per token, and at a speed of 2,000 tokens/s this is about 16 TB/s of weight reads — one order of magnitude from the stated bandwidth, so the estimate appears to rely on an engineering model rather than a random marketing number. The only independent factual anchor pertains to a different chip: the SpinPU-ED01 with 120 MRAM banks passed third-party verification — a bandwidth density of 0.105 TB/(mm²·s) was measured, end-to-end model inference was performed, and 24 hours of stable operation were achieved, but this is a different chip and a different metric, not uHBM metrics. The lineup exists at the architectural design level, the first engineering generation is in the pre-fab pipeline, and the process node, timelines, and pricing have not been announced, so any comparisons with HBM3E remain hypothetical until tape-out results.

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