AMD has provided a detailed description of the MEXT (MEXT Predictive Memory) technology, acquired along with startup Mext in June 2026: a software layer moves 'cold' memory pages from DRAM to NVMe flash on Epyc servers, while a transformer model, trained directly on the server without a GPU, pre-fetches them back into RAM before the application accesses them. According to AMD measurements, Apache Spark retains 99% performance when half of the DRAM is replaced, while Synopsys PrimeTime retains 95% with half of the DRAM and 80% with only a quarter of the DRAM. MEXT works only on AMD hardware and is distributed via license through OEM partners.

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What happened

AMD published a detailed description of MEXT Predictive Memory, a software solution the company acquired in June 2026 along with startup Mext. The MEXT layer moves rarely used, 'cold,' memory pages from DRAM to a dedicated NVMe disk, while an embedded transformer model—an LLM-like model that predicts not the next token, but the next needed memory page—pre-fetches them back into DRAM before the application accesses them. The model is trained on-device on a single Epyc core, without a GPU. Deployment requires a dedicated NVMe disk, disabled swap, and two free CPU cores: one for the AI engine and one for the daemon. According to AMD's own measurements, Apache Spark retained 99% performance when half of the DRAM was replaced, while Synopsys PrimeTime retained 95% with half of the DRAM and 80% with only a quarter of the DRAM. The solution works only on AMD hardware and is sold via license through the OEM channel.

Context

The mechanics of MEXT rely on the TPP research (arXiv:2206.02878), which states that in a two-minute window, 55–80% of server memory is idle—the technology leverages this 'cold' reserve. The economic backdrop is DRAM shortage and price increases: Bloomberg forecasts a memory chip shortage until 2030, and memory accounts for 60–90% of the cost of large servers. NVMe flash is approximately 50 times cheaper per bit and 30 times more power-efficient than DRAM, but roughly 500 times slower—so the entire structure relies on prediction accuracy, and every model miss results in a synchronous page load from flash. AMD states that the technology has already been deployed on 145 systems; the claim of $5 million savings on these systems was made by the former CEO of Mext, who is now a CVP at AMD.

Why this matters for the industry

For the industry, MEXT is AMD's attempt to capitalize on the DRAM shortage and rising prices: selling servers with half the memory volume as a licensed option and opening a new price segment for EDA, databases, analytics, and agentic AI pipelines, where memory is 60–90% of system cost. This is a claim to a price shift in server memory economics, not just a new feature: if the predictor's accuracy is confirmed, DRAM+NVMe tiering with a trainable model could become a standard option for Epyc servers and push competitors, including Intel, to develop similar solutions. The limitation is that the current evidence base consists of measurements by the vendor itself on two workloads, and access to the product is only possible via OEM license on AMD hardware.

Why this matters for users

For readers, this is a clear example of transformers working beyond LLMs: the model predicts memory pages, not tokens, and is trained directly on the server in seconds. If the technology takes hold, servers with half the DRAM will be significantly cheaper with nearly the same performance—this is primarily important for those deploying their AI workloads on-premises. There is currently no direct access to MEXT: no public API or distribution exists, only an OEM license on AMD hardware. A reasonable first step is to profile your own workloads for the share of idle memory, which according to TPP logic reaches 55–80% in a two-minute window; with an Epyc server with a free NVMe disk and two cores, a cautious pilot on a dedicated stand is possible, measuring your own hit rates and tail latencies and comparing TCO with buying DRAM.

What is currently unknown / limitations

All performance figures are measurements by an interested vendor on two workloads, Apache Spark and Synopsys PrimeTime, without disclosing configurations, run durations, variance, or a comparative baseline; both selected workloads have relatively regular memory access patterns. AMD does not publish the predictor's hit rate or p50/p99 tail latencies, although flash is ~500 times slower than DRAM and every miss turns into a synchronous page fetch from NVMe. The stated economics, including the $5 million savings on 145 systems, were announced by the former CEO of Mext, now CVP at AMD, and have not been confirmed by an independent audit. License prices and availability timelines have not been disclosed; a dedicated NVMe disk, disabled swap, and two CPU cores are required, the product works only on AMD hardware, and there is no public API yet.

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